The invention pertains to methods of reducing non-planarity of surfaces, and, in particular applications, pertains to methods of forming materials over uneven surface topologies. In exemplary embodiments, the invention pertains to methods of forming insulative materials over and between conductive lines.
A prior art method of forming insulative material over and between conductive lines is described with reference to FIGS. 1-4. Referring to FIG. 1, a fragment 10 is illustrated at a preliminary processing step. Fragment 10 comprises a substrate 12 having an upper surface 15. Conductive lines 14, 16, 18 and 20 are formed over upper surface 15. Substrate 12 can comprise an insulative material such as, for example, borophosphosilicate glass (BPSG), silicon dioxide and/or silicon nitride. Substrate 12 can further include a portion of a semiconductive material wafer. To aid in interpretation of the claims that follow, the term xe2x80x9csemiconductive substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Conductive lines 14, 16, 18 and 20 can comprise conductively doped polysilicon and/or metals. Exemplary metals are aluminum, aluminum alloys, copper, copper alloys, tungsten and titanium. In particular aspects, conductive lines 14, 16, 18 and 20 can consist essentially of metals (either in alloy form or elemental form). Such metallic conductive lines can further correspond to a first elevational level of metallic conductive lines formed over a semiconductive substrate (a so-called xe2x80x9cmetal 1xe2x80x9d layer).
An insulative material 22 is formed over and between conductive lines 14, 16, 18 and 20. Material 22 can comprise, for example, silicon dioxide, and can be formed by chemical vapor deposition (CVD) utilizing a tetraorthosilicate (TEOS) precursor. Such CVD can occur at or below 400xc2x0 C., which can be advantageous to avoid melting of any metals incorporated into lines 14, 16, 18 and 20.
In the construction of FIG. 1, material 22 is formed over an uneven surface topology. Such uneven surface topology comprises outward projecting features consisting of lines 14, 16, 18 and 20, and valleys 24 consisting of spaces between lines 14, 16, 18 and 20. The deposited material 22 comprises outwardly projecting features 26 over conductive lines 14, 16, 18 and 20, and comprises gaps 28 over valleys 24. The gaps 28 have bottoms 23 extending elevationally beneath uppermost surfaces of conductive lines 14, 16, 18 and 20. Material 22 thus comprises a substantially non-planar outer surface 30 which extends over lines 14, 16, 18 and 20, and within gaps 28. Outer surface 30 comprises substantially horizontal upper surfaces 27 and substantially vertical sidewall surfaces 29.
It is noted that a continuing goal of semiconductor fabrication is to decrease the size of circuit elements. Lines 14, 16, 18 and 20 have respective widths xe2x80x9cYxe2x80x9d (shown for lines 16 and 18), and gaps 24 have about the same respective widths xe2x80x9cYxe2x80x9d. The width xe2x80x9cYxe2x80x9d will typically correspond to about a minimum feature width achievable during fabrication of lines 14, 16, 18 and 20.
Present semiconductor fabrication processes achieve constructions in which xe2x80x9cYxe2x80x9d is about 0.5 micron and, of course, a goal of future processes is to achieve constructions in which xe2x80x9cYxe2x80x9d is less than 0.5 micron. The 0.5 micron spacing corresponding to gaps 24 is too tight to allow material 22 to form conformity over and between lines 14, 16, 18 and 20. If material 22 formed conformally over and between lines 14, 16, 18 and 20, gaps 28 would be relatively wide shallow gaps. Instead gaps 28 have a high aspect ratio (i.e., an aspect ratio of at least about 3), which complicates further processing. Specifically, it is frequently desired to planarize material 22 to form material 22 into a substantially level base which can be utilized to support additional circuitry formed above it. A common method of planarization is chemical-mechanical polishing. However, such will not work effectively on the material 22 shown in FIG. 1 because the chemical-mechanical processing will be stopped before removing the material of lines 14, 16, 18 and 20, and hence before reaching the bottoms 23 of gaps 28. Accordingly, portions of gaps 28 will remain after a chemical-mechanical polishing process, and will cause a remaining portion of material 22 to have a non-planar outer surface.
In an effort to overcome the above-described difficulties in planarizing material 22, the processing of FIGS. 2-4 is employed. FIG. 2 illustrates fragment 10 after material 22 has been subjected to an anisotropic etch. Such etch forms material 22 into sidewall spacers 40 extending along sidewalls of conductive lines 14, 16, 18 and 20. The etching also widens gaps 28. Additionally, the etching can, as shown, extend gaps 28 into underlying material 12. The extent to which gaps 28 penetrate into material 12 depends on how selective the anisotropic etch is for material 22 relative to the material of substrate 12. If material 22 and substrate 12 comprise the same material (such as, for example, BPSG), then the etch will be non-selective for material 22 relative to the underlying material substrate 12.
Referring to FIG. 3 additional layers 42 and 44 are formed over conductive lines 14, 16, 18 and 20, and within gaps 28. Materials 42 and 44 comprise insulative materials such as, for example, silicon dioxide or BPSG. Materials 22 and 24 fill gaps 28 to a level above line 14, 16, 18 and 20.
Referring to FIG. 4, materials 42 and 44 can be subjected to chemical-mechanical polishing to form a planarized insulative material having an upper surface above lines 14, 16, 18 and 20.
It would be desirable to develop alternative methods for forming a planarized material. More generally, it would be desirable to develop new methods of forming and planarizing materials formed over uneven surface topologies.
In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A layer of material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the outwardly projecting features of the surface topology and has a gap over the valley. The layer is etched. The etching forms protective material within the gap while removing an outermost surface of the layer. The etching substantially does not remove the material from the bottom of the gap.
In another aspect, the invention encompasses a semiconductor processing method of forming a material over metal-comprising lines. A first insulative material substrate is provided. A pair of spaced metal-comprising lines are formed over the substrate. The spaced metal-comprising lines define an uneven surface topology which comprises the lines and a valley between the lines. A layer of second insulative material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the lines and having a gap over the valley. The layer of second insulative material is subjected to an etch which forms a protective material at the bottom of the gap. The protective material substantially prevents the second insulative material from being etched from the bottom of the gap.